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SWAN/NASCENT Entrepreneur In Residence PDF Print E-mail

 

The Southwest Academy for Nanoelectronics (SWAN) and the NSF Nanosystems Engineering Research Center for Nanomanufacturing Systems for Mobile Computing and Mobile Energy Technologies (NASCENT) have selected Leo Mathew as the first SWAN/NASCENT Entrepreneur In Residence. Mathew is the co-founder and CEO of Applied Novel Devices (A.N.D.), a tech startup developing CMOS devices beyond 14 nanometers, FinFETS, Discrete Power Devices with low on-Resistance, flexible and high efficiency silicon photovoltaic architectures, and integrated passives. A.N.D. collaborates closely with NASCENT and SWAN, and has recently joined the NASCENT Center as a member of the NASCENT Industrial Affiliates Program. A.N.D is headquartered at UT Austin’s Austin Technology Incubator.

In his role as the SWAN/NASCENT Entrepreneur in Residence, Mathew will mentor and guide SWAN and NASCENT faculty and students who are exploring early stage commercialization of the technologies they develop. In response to his selection, Mathew said, “NASCENT and SWAN are both exciting centers at the forefront of nanotechnology and electronics. It’s an honor to be selected as their Entrepreneur In Residence.”

“We are excited to be working with Leo,” said Prof. S.V. Sreenivasan, the Co-Director of the NASCENT Center. “His knowledge and skills will be an invaluable reference to the NASCENT and SWAN faculty and students. Leo will help us to accelerate our commercialization efforts.” Prof. Sanjay Banerjee, the SWAN Director, said “Leo is an exciting and dynamic entrepreneur, and we are lucky to have him as our Entrepreneur-In-Residence. His device physics expertise and his business acumen make him ideal for the role.”

Leo Mathew has more than 20 years of experience in the semiconductor industry. He completed his masters in micro-electronics process technology at Arizona State University and began his career at Motorola/On Semi/Freescale semiconductors. He has over 50 issued patents covering Power, RF-Analog, CMOS, Solar and LED devices, and has designed and brought to market over 40 new power MOSFET products. He is the recipient of the Distinguished Innovator award at Freescale and was recognized with the EE Times ACE Award for Innovator of the Year in 2006 for his contributions to new multi-gate devices. In 2008 he Co-Founded A.N.D., which develops innovative device architectures and new process technologies to overcome semiconductor devices scaling limits.

Monolithic Single-Mode DFB Laser Array with Precise Wavelength Control for Optoelectronic Integration using an Equivalent Phase Shift Method Abstract

Fast and slow transient charging in various III-V field-effect transistors with atomic-layer-deposited-Al2O3 gate dielectric Abstract

 

ABOUT SWAN

The South West Academy of Nanoelectronics (SWAN) is one of the three centers created in 2006 by the Semiconductor Research Corporation Nanoelectronics Research Initiative (SRC-NRI) to find a replacement to conventional metal oxide semiconductor field effect transistors.  SRC-NRI is a consortium of AMD, Freescale, IBM, Intel, MICRON, TI.  Matching funds have been provided by the State of Texas Emerging Technology Fund.  SWAN is headquartered at the Microelectronics Research Center at the University of Texas at Austin.

ABOUT NASCENT

The NSF Nanosystems Engineering Research Center (NERC) for Nanomanufacturing Systems for Mobile Computing and Mobile Energy Technologies (NASCENT) was funded in September, 2012. The center develops high throughput, high yield and versatile nanomanufacturing systems to take nano-science discoveries from the lab to the marketplace.  The Center is headquartered at the Microelectronics Research Center at the University of Texas at Austin, and includes two partner institutions – the University of California at Berkeley and the University of New Mexico. Also included are Seoul National University in South Korea and the Indian Institute of Science.

 


 

About SWAN

SWAN is one of the three centers created in 2006 by the Semiconductor Research Corporation Nanoelectronics Research Initiative ( SRC-NRI) to find a replacement to conventional metal oxide semiconductor field effect transistors.

SRC-NRI is a consortium of TI, Freescale, AMD, MICRON, Intel and IBM.

Matching funds have been provided by the State of Texas Emerging Technology Fund

The Microelectronics Research Center at The University of Texas at Austin (MRC) provides opportunities to perform research in novel materials of interest to the IC industry, optoelectronics and nanophotonics, novel electronic devices and nano-structures, interconnects and packaging.

The UT-MRC laboratories are located at the JJ Pickle Research Campus, in northwest Austin.

The UT-MRC laboratories reach users from many different backgrounds: electronics, optics, physics, chemistry, astronomy, as well as chemical, mechanical, and petroleum engineering. Lab users include The University of Texas as well as non-UT academic and industrial users. The MRC is more than a clean room with open-access to advanced nano-fabrication equipment. - It is a community of scientists who work together to share knowledge.

Other micro/nano-fabrication facilities include sputter, e-beam and plasma deposition for Al, silicide's and dielectrics, reactive ion etching, rapid thermal processing and oxidation/diffusion furnaces for Si, Si-Ge and High-K dielectrics, LPCVD for poly-silicon, oxides, nitrides and numerous wet chemistry stations. The characterization laboratories contain apparatus for comprehensive optical and electrical measurement.

A professional and experienced cadre of facilities and equipment technicians and engineers, who not only maintain the tools and provide training to new users, but are also able to help support and collaborate with you concerning your project.

The facilites include 12,000 sq. ft. of Class 100 and Class 1000 clean-room space for Si. III-V and soft material processing. The clean roomalso contains a JEL - 6000F/E based electron beam lithography system capable of 20nm resolution on masks, small substrates and 8" wafers. This e-beam system is used to generate templates for the Step and Flash Imprint Lithography tool. The S-FIL process is a nano-imprint scheme or patterning of features in the sub-micron regime with the ability to perform layer-to-layer alignment through a transparent template to sub-tenth micron accuracy.

 
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